1. Field of the Invention
The present invention relates generally to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of distributing a common clock signal for an integrated circuit design within timing constraints that are determined by the selection and arrangement of clocked logic elements in the circuit design.
2. Description of Related Art
Clock signals are widely used in integrated circuit designs to coordinate generation and propagation of logic functions across an integrated circuit die. The distribution of a clock signal to various locations across the integrated circuit die is an important aspect of the circuit design. The difference in the arrival time of a common clock signal at various locations in the physical layout of an integrated circuit design, or floorplan, is called clock skew. The variation in the clock period at various locations in the floorplan is called jitter. Both clock skew and clock jitter may result in decreased performance capability in terms of maximum operating frequency and in circuit malfunction from setup and hold time violations. Previous methods of distributing a common clock signal for an integrated circuit design typically avoid clock skew by a balanced clock tree design and avoid clock jitter by shielding clock signal wires from crosstalk.